--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : ISE
--  /   /         Filename : test_alu.vhw
-- /___/   /\     Timestamp : Tue Dec 08 10:06:17 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: test_alu
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_alu IS
END test_alu;

ARCHITECTURE testbench_arch OF test_alu IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

    COMPONENT ALU
        PORT (
            function_code : In std_logic_vector (2 DownTo 0);
            RegA : In std_logic_vector (15 DownTo 0);
            RegB : In std_logic_vector (15 DownTo 0);
            result : Out std_logic_vector (15 DownTo 0);
            zero : Out std_logic;
            carry : Out std_logic
        );
    END COMPONENT;

    SIGNAL function_code : std_logic_vector (2 DownTo 0) := "000";
    SIGNAL RegA : std_logic_vector (15 DownTo 0) := "0000000000000000";
    SIGNAL RegB : std_logic_vector (15 DownTo 0) := "0000000000000000";
    SIGNAL result : std_logic_vector (15 DownTo 0) := "0000000000000000";
    SIGNAL zero : std_logic := '0';
    SIGNAL carry : std_logic := '0';

    BEGIN
        UUT : ALU
        PORT MAP (
            function_code => function_code,
            RegA => RegA,
            RegB => RegB,
            result => result,
            zero => zero,
            carry => carry
        );

        PROCESS
            BEGIN
                -- -------------  Current Time:  100ns
                WAIT FOR 100 ns;
                RegA <= "0000000000001000";
                RegB <= "0000000000000010";
                -- -------------------------------------
                -- -------------  Current Time:  200ns
                WAIT FOR 100 ns;
                function_code <= "001";
                RegA <= "0000000000000100";
                RegB <= "0000000000000100";
                -- -------------------------------------
                -- -------------  Current Time:  300ns
                WAIT FOR 100 ns;
                function_code <= "010";
                RegA <= "0000000000010000";
                RegB <= "0000000000001000";
                -- -------------------------------------
                -- -------------  Current Time:  400ns
                WAIT FOR 100 ns;
                function_code <= "011";
                RegA <= "0000000000000010";
                RegB <= "0000000001000000";
                -- -------------------------------------
                -- -------------  Current Time:  500ns
                WAIT FOR 100 ns;
                function_code <= "100";
                RegA <= "0000000001000000";
                RegB <= "0000000000010000";
                -- -------------------------------------
                -- -------------  Current Time:  600ns
                WAIT FOR 100 ns;
                function_code <= "101";
                RegA <= "0000000100000000";
                RegB <= "0000000000100000";
                -- -------------------------------------
                -- -------------  Current Time:  700ns
                WAIT FOR 100 ns;
                function_code <= "110";
                RegA <= "0000000000100000";
                RegB <= "0000000000000010";
                -- -------------------------------------
                -- -------------  Current Time:  800ns
                WAIT FOR 100 ns;
                function_code <= "111";
                RegA <= "0000000000000100";
                RegB <= "0000000000000100";
                -- -------------------------------------
                -- -------------  Current Time:  900ns
                WAIT FOR 100 ns;
                function_code <= "000";
                RegA <= "0000000000000000";
                RegB <= "0000000000000000";
                -- -------------------------------------
                WAIT FOR 1100 ns;

            END PROCESS;

    END testbench_arch;

